The invention relates to error detection in the representation of words by bits and in particular to the use of a variable number of parity bits associated with the words.
Numerous schemes are available for error checking of words during their storage or transmission. These schemes vary from a fixed number of parity bits associated with the word, to storing the word in more than one location for comparison.
U.S. Pat. No. 4,530,050 to Fukunaga et al. describes variable length instructions that permit operand specifiers to be shared. U.S. Pat. No. 4,450,562 to Wacyk et al, shows a two level parity error correctionsystem with a fixed number of parity bits.
Many times, an instruction word requires less than the architected number of bits to express the word. In such cases, a fixed number of parity bits is used for all the words, regardless of its size. The parity bits permit detection and potentially correction of words dependent on the number of bits. Usually, there are instructions approaching the architected number of bits that serve to limit the number of fixed parity bits used for all the words, thus reducing the number of bits in error that are detectable and/or correctable for all the words.
Instruction words are usually stored in static RAM (random access memory) chips or imbedded arrays which are very fast and permit a processor to run at a fast rate. Such RAMs also have a high failure rate and can severely influence a processor's ability to detect and isolate its own errors. Since the instruction words are not usually altered by the processor, but simply read and executed, parity is generated at development time and stored with the control word, so the parity bits are also subject to the same error rate as the word.